@article{'BHO4',
title = { Verification and validation meet planning and scheduling },
author = {Bensalem, Saddek and Havelund, Klaus and Orlandini, Andrea},
year = {2014},
journal = {{STTT}},
number = {1},
pages = {1--12},
volume = {16},
team = {DCS, RSD},
}
bibtex
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- 28 novembre 2024 Grégoire Bussone: Réduire les copies et l'utilisation mémoire dans les langages synchrones
- 2 décembre 2024 Thomas Vigouroux: Analyses quantitatives pour les attaquants adaptatifs (Phd)
- 12 décembre 2024 Lucas Bueri: Tba (Phd)
- 12 décembre 2024 Bob Aubouin-pairault: Tba (Phd)
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- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Self-stabilizing Synchronous Unison in Directed Networks
- Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne: A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
- Aina Rasoldier, Jacques Combaz, Alain Girault, Kevin Marquet, Sophie Quinton: Assessing the Potential of Carpooling for Reducing Vehicle Kilometers Traveled
- Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard: Formally Verifying Optimizations with Block Simulations
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- [Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
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- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Towards New Frontiers in Multi-Core Response Time Analysis ?
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences