@article{SBM0,
title = { Certified and Efficient Instruction Scheduling: Application to Interlocked VLIW Processors },
author = {Six, Cyril and Boulm\'e, Sylvain and Monniaux, David},
month = {nov},
year = {2020},
address = {New York, NY, USA},
journal = {Proc. ACM Program. Lang.},
publisher = {Association for Computing Machinery},
series = {OOPSLA 2020},
volume = {4},
team = {axe_FormalProofs, axe_SharedResources, PACSS},
pdf = {https://hal.archives-ouvertes.fr/hal-02185883v3/file/extended_main.pdf},
abstract = {CompCert is a moderately optimizing C compiler with a formal, machine-checked, proof of correctness: after successful compilation, the assembly code has a behavior faithful to the source code. Previously, it only supported target instruction sets with sequential semantics, and did not attempt reordering instructions for optimization. We present here a CompCert backend for a VLIW core (i.e. with explicit parallelism at the instruction level), the first CompCert backend providing scalable and efficient instruction scheduling. Furthermore, its highly modular implementation can be easily adapted to other VLIW or non-VLIW pipelined processors.},
}
