Wednesday 29th January 2014, between 5pm and 6 pm, Matthieu Moy (Verimag) gives a Lecture at collège de France on « Virtual prototyping of systems on chip for an efficient and faithful simulation »
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A Lecture at collège de France by Matthieu Moy
View online : http://www.college-de-france.fr/sit...
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Seminars
- Seminars
- 28 November 2024 Grégoire Bussone: Reducing copies and memory consumption in synchronous languages
- 2 December 2024 Thomas Vigouroux: Quantitative analysis for adaptive attackers (Phd)
- 12 December 2024 Lucas Bueri: Tba (Phd)
- 12 December 2024 Bob Aubouin-pairault: (Phd)
New publications
- Some Recent Publications
- David Monniaux, Léo Gourdin, Sylvain Boulmé, Olivier Lebeltel: Testing a Formally Verified Compiler
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Self-stabilizing Synchronous Unison in Directed Networks
- Florence Maraninchi: Revisiting "Good" Software Design Principles To Shape Undone Computer Science Topics
- Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard: Formally Verifying Optimizations with Block Simulations
Jobs and internships
- Jobs and internships
- [Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
- PERSYVAL Master 2 Scholarships
- [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
- [Funded PhD] Quantitative analysis of software security against adaptive attacks
- [Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Towards New Frontiers in Multi-Core Response Time Analysis?
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences